Intel has announced a new multi-core processor, and the fact that it was introduced at the International Supercomputing Conference (ISC) instead of the consumer-oriented Computex show taking place at the same time should be an indication of its target market.
“Knight’s Corner” is the codename for this processor, called a many integrated core (MIC) architecture. It consists of 50 x86 cores crammed onto a single 22-nanometer-process chip smaller than a postage stamp.
Knight’s Corner is different from the experimental 48-core processor that Intel (NASDAQ: INTC) had previously shipped out, which was built on older x86 core designs and not very parallel. The 48-core processor was often referred to as a single-chip cloud-computing processor and meant for massive cloud and virtualization scenarios.
In that regard, Knight’s Corner bears more resemblance to Larrabee, the company’s ill-fated attempt at a GPU, than the 48-core processor did. Intel’s Larrabee sought to bring massive parallelism to the x86 architecture. Just last week Intel said it had scuttled Larrabee as a graphics program but added that it planned to repurpose the hardware as a high-performance computing platform.
“Intel’s Xeon processors, and now our new Intel Many Integrated Core architecture products, will further push the boundaries of science and discovery as Intel accelerates solutions to some of humanity’s most challenging problems,” Kirk Skaugen, vice president and general manager of Intel’s Data Center Group, said in a statement.
Intel is already making design and development kits, codenamed “Knight’s Ferry,” available to select developers. A Knight’s Ferry card looks like a high-end graphics card and plugs into a PC, but it has 32 cores running at 1.2GHz and can run up to 128 threads at one time. Beginning in the second half of 2010, Intel will expand the program to deliver developer tools for Intel MIC architecture to move developers.
Already the company has helped some of its most elite customers begin experimenting with Knight’s Corner.
“The CERN openlab team was able to migrate a complex C++ parallel benchmark to the Intel MIC software development platform in just a few days,” CERN CTO Sverre Jarp said in a statement. “The familiar hardware programming model allowed us to get the software running much faster than expected.”
The mainstream market is still trying to get its arms around quad-core processors, but the market Knight’s Corner will serve has a better grip on massive parallelism, according to Nathan Brookwood, research fellow with Insight 64.
“These are targeted at high-performance computing where people have been building apps for years that use hundreds of processors,” he told InternetNews.com. “If you are in the HPC community and doing things that require multiple teraflops of processing power, then you have figured out ways to do this. That is not a big market, but it can be a lucrative one.”
There will be two advantages to a 50-core chip over, say, a server with six of Intel’s eight-core Xeon 7500 processors, Brookwood noted.
“This chip will use a lot of power but not nearly as much power as a bunch of quad-core x86s. So performance per watt with this approach should be better,” he said.
And it could be better because people are using finely tuned algorithms here that get performance you can’t match with multiple physical chips that have to talk through I/O buses.
“For some algorithms, if you can get all the right data in the cache at the same time and get 50 cores sharing that data, you can get performance you couldn’t match [with regular multi-core chips],” Brookwood said.