This time, the chip giant not only cuts away functions that are regarded as non-essential, but it is actively adjusting hardware in order to prevent the industry (and as a consequence, the users) from anticipating upcoming features like DDR2-667 and FSB 1066.
Of course we tried to get some DDR2-667 DIMMs in order to see what they can do. The small memory makers do not have these chips yet, while the big ones claimed not to have any samples for the press. Interesting, however, is the fact that a well known memory specialist will launch its DDR2-667 memory as early as July 7.
Anyways, as long as there is no chipset that supports DDR2-667, these fast DDR2 DIMMs only make sense if users can overclock their systems. What Intel did is implement an overclocking limiter to the MCH chips: If the CPU clock exceeds the threshold (we determined that this is 10% over specification), the required PLL (Phase Lock Loop) will reset and won't refuse to lock that frequency. Basically that is a very simple way of throwing a spanner in the works, as it causes a system crash. Decent motherboards automatically restart and you may try again. The easy way would be to limit all overclocking ambitions to 10% max, but now that Intel added this extra obstacle, I somehow felt compelled to break some barriers.
With the chipset's A stepping, a register could be used to remove the overclocking lock. The current stepping (B1), however, does not allow for the 'feature' to be disabled any more.
However, we know of two motherboard makers that have already managed to override the overclocking limiter successfully: Asus and Gigabyte. And it isn't really difficult, but it's a shame to think that smaller manufacturers simply don't have enough manpower make such a venture possible.
Usually, the PLL is initialized at system startup in order to lock the frequency that is stored in BIOS. Here's where we need to start, since it won't lock frequencies that exceed the internal limiter. Intel accomplished this by linking the PLL to the assertion time of the Northbridge reset signal.
After adding a little hardware modification, the two companies mentioned above managed to pass control over the PLL ready time to the BIOS. Each frequency has a different PLL locking time that the BIOS software needs to be aware of. Based on that information, the BIOS will now adjust the period of time the system remains in reset mode until the PLL successfully locks the clock.