How does memory work - is it a load of transistors like a CPU or is it something else?
Also, how do they make some memory run faster than others? is it a new architecture, or a 'die shrink' or equivalent?
mostly would like to know about physical construction etc.
Thanks
O
(its here coz theres no 'memory' forum, and basically you guys in here know the most anyway!)
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The memory cell (used to store one bit) in Dynamic RAM consists of one capacitor and one transistor. The two devices are generally stacked vertically these days to provide higher density.
The memory cell in static RAM, which is used in caches, generally consists of six transistors. It is called static because it does not need refreshing like dynamic RAM does. This is because the charge in the capacitor which holds the bit's data will leak over time since the transistor has a finite resistance.
I can provide links to some more detailed descriptions and diagrams if you are interested.
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I remember learning about memory a while ago... It is a "Flip-Flop" or something and just consists of "And" and "Or" gates or something like that, never liked that subject!
A typical SDRAM chip (or most memory in general) is manufactured just like a CPU. It's a little cheaper because the process is shorter, but for all intents and purposes, you can consider them the same. The biggest hurdle in RAM design is the capacitor- shrinking smaller and smaller in silicon is very good for transistors, but very bad for capacitors. The reason they have to be refreshed so fast is that the capacitor will leak out through the silicon substrate (which is slightly doped and conductive and used as a system ground) and the connecting transistors. FYI, for anyone reading this who doesn't know, "doping" is the act of adding impurities to the semiconductor. This subtly changes the electrical properties and increases the conductivity, making things like transistors possible. Depending on whether the dopant is an n (~adds electrons) or p (~adds a "hole" or lack of electron) type, the junction between them becomes a barrier, or a wire, depending on what the charge is. In a MOSFET, current in the gate attracts electrons to a region, temporarily changing it's effective doping from an n to p or a p to n type region, and a conductive channel forms. In a CMOS process, both happen and minimize current draw. It's hard to explain in words... Anyhow, I digress!
As Gomez stated, each RAM bit consists of a capacitor and a small number of transistors. Each bit is addressed individually (an AND gate, essentially, that opens a data pipe from the capacitor to the reading logic) a couple million times a second, read before the capacitor discharges, and that value written right back to it through the same AND gate. If power is cut, the RAM almost instantly loses all data. Old RAM modules were more forgiving- lasting a few seconds. I don't know values on today's, but I think it's in the microseconds, or maybe even less. FYI, silicon transistors look nothing like the circuit diagrams you're used to seeing- it's more of a jumble. It's the layout of the doped layers and gates, etc, that really makes it work. A capacitor is essentially just a large doped region designed to have much more capacitance than, say, the connect pad of the transistors connected to it. But fundamentally it's identical to them.
To make a faster RAM, the transistors and wires have to get smaller, but the smaller the chip gets, the exponentially smaller the capacitor gets and likewise, the capacitince. New techniques like ion implanting and SOI make the current 500MHz+ speeds possible, but there are still limitations- every time a die shrink makes the gate width and other insulating barriers get smaller, the leak current from the capacitor discharges it faster, and it has to be refresed quicker, in a vicious cycle requiring more speed to operate. A couple years ago, there was a breakthrough new design that allowed each RAM bit to use about half the previous number of transistors- it's because of this that chips got much much smaller without having to decrease the capacitor size. When chips get smaller, more can fit on a wafer, and the more on a wafer, the cheaper it is to manufacture- that's why DIMMs are so cheap and SIMMs still ridiculously expensive; IIRC, the SIMMs still have to be made the old way with the old wasteful tranistor design. I'll see if I can find a digram or SEM photo of an actual bit cell somewhere
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[This message has been edited by grover (edited 06-29-2001).]
I can't find any good photos... here's a screenshot of a design program. The transistor, as seen in silicon, is the green red and blue square in the lower corner- the green region with two black squares and the red going through it is a MOSFET. The red is the gate.
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[This message has been edited by grover (edited 06-29-2001).]
wow.. slight brain overload at times but also v useful.. thanks guys
so does it look like there is a definable limit to the speed we can expect current memory production technology to top out at? we dont want high mulitpliers, we want high FSB! when will i get 1ghz fsb??
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Whoops, sorry about that, haha... ummm... here it is again without any words you didn't use in your first post, Oliy
Memory is a load of transistors created in silicon, just like a CPU. They're made to go faster, cheaper and larger by shrinking the die, just like for CPUs only they have the added problem of continually shrinking capacitors, because capacitors don't work well when they get that small.
Bear in mind that CPUs have built-in memory as well; in fact, fast cache memory (like L1 and L2) is all over a CPU and integral to it, and operates at the same speed as the CPU itself. There are tens in not hundreds or thousands of smaller, lesser known caches all throughout the rest of the chip too, saving small bits of data here and there while other parts are being crunched. So it isn't to say that we can't have 1.7GHz memory, it's just not feasible to have a 1.7GHz DIMM quite yet due to other problems unrelated to the actual chip.
Found some better pictures, BTW. Here's a trench capacitor DRAM, like the kind I described up above. The first paragraph of this article gives an excellent explanation of how the process works.
This is an experimental design, but gives you a good idea of what a typical stacked DRAM cell looks like. The capacitors are on top, logic and lines on the bottom:
[This message has been edited by grover (edited 06-29-2001).]
[This message has been edited by grover (edited 06-29-2001).]
Signal degradation is a problem when things get that fast. There are already tons of things implemented to make sure the RAM gets a strong noise-free signal. The long traces on a motherboard tend to hamper also. That is why the same DDR SDRAM chip on a video card can do 200 while it can only do 150 on a motherboard. Suppose for a second that the memory controller, the memory, and the controller were all in one chip. It'd be very expensive, and not very upgradeable, but it'd be fast. Just look at the large cache Xeons. Intel has gotta be kidding theirselves on this one. You make trade-offs if you wat to make money. Anywho, there's my $.17.
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only they have the added problem of continually shrinking capacitors, because capacitors don't work well when they get that small. 
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