Feasibility of dual Celer-mines
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Thread: Feasibility of dual Celer-mines

  1. #1
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    Feasibility of dual Celer-mines

    I am planning to get a BP6 with dual celly 366's o/c to 550 on it from a local HWC patron. I was wondering some of your opinions on whether it would be feasible to upgrade the processors later to dual Celeron II 566's running at 850mhz (probably with dual peltier/liquid coolant system installed).

    From what I've heard so far the 566's don't have much trouble doing 850 with the right cooling. I'm wondering if the 666mhz model would go to 1000mhz with the right cooling...hmm...

    How does that sound to you guys? Dual celeron 2 566's at 850...feasible? Hope so!

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  2. #2
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    Yes that would be great.
    I suppose your goin to use the adapter thats converts the formats.(ppga-fcpga)
    With water and peltiers you could expect 850 maybe 900 with upped voltage.
    But i'm not sure how the BP6 is gonna stand up to the cele2's cos of the multi's
    Look for a BP6-2


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  3. #3
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    There's a 666MHz celermine? made by intel? coincidence?? i think not...

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  4. #4
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    Did they change SMP support in celermines? I was under the impression that coppermines would work in the BP6, and therefore celly2's would as well. BP6-2? never knew there existed such a thing...


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  5. #5
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    www.BP6.com has a joke picture of the BP6-2. Wish I had one of those.

  6. #6
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    What's that Diablo....

    CPUs must support SMP?, you astound me. I would have thought someone coding a new OS would know all you have to do to support SMP is plug, glue or tape two or more CPUs to a board.

    Glad to see you finally learned something.



    DMMD

  7. #7
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    DMMD, you're such an ***. I'm sick of your attitude. You flatly assume that I know nothing about a topic, when you know nothing about my background or experience. You do that to everyone about everything. Get off your high horse and quit talking down to people. There are people that know immensely more than you, but you still behave like some IT moron who read a user's manual and took it upon himself to educate the populace.

    You can take all your supposed knowledge and expertise, ball it up, turn it sideways, and shove it straight up your ***.

    "There are only two things that are infinite: the universe and human stupidity, and I'm not sure about the universe." - Albert Einstein

  8. #8
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    Ok, Ok, calm down fellas.... Everybody take a deep breath and relax...... ahhhhhh

    Now, back to the subject of this post. From what I have been able to gather from researching this subject myself, it would appear that Intel has disabled SMP in the new Celermines (Culerons? ). This time it's not a matter of a simple pin location change, they apparently have not connected the SMP enable line from the core to the FC-PGA carrier.

    I do have to say that I have no first-hand knowledge that this is true. I sure as hell hope it's not.
    _________________________"Give a man a fish and he will eat for a day,
    Teach a man to fish and his wife will divorce
    him, get the house, the kids, the boat, his rods
    and reels, and he will learn to drink..."

  9. #9
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    Quote:
    "DMMD, try not to say things that gets the others here all wind up "
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  10. #10
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    I don't assume anything:

    Do you know what I do.

    Do you denie that NOW you understand that CPUs and OS and Ap and Algorythm must be amenable to Parellization, before SMP is realizable. You learned that because I spanked you. And I did so because I am tired of you pukes reading diatribe and then recapitulating it (blowin' chunks) in a setting supposedly for helping people, not supporting your own pittiful self-esteem.

    I am envolved on this forum only for the purpose of helping people, in 15 mins. I'll be taking a blood clot out of a pt's head. I don't care about you, or that other silly thing at CPU, I just care about good and helpful information getting to the people that ask for it.

    You are the worst possible posters on such a forum.

    You read and interpret with your puny experience and skills, then post. And people listen and believe the crap you puke out.

    You're Coding your own operating sytem?

    I write code.

    I consult for companies focussed on implementing aps that will help people. And I know what it takes to write such code.

    Those that know me, know I donot ride a high horse: but I spank the hell out of little pukes like you that prettend to know something, when they donot, and more importantly, attempt to shed their ignorance on others.

    DMMD

    [This message has been edited by DMMD (edited 04-09-2000).]

    [This message has been edited by DMMD (edited 04-09-2000).]

  11. #11
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    The madder they are, the worse they spell..(sigh)

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  12. #12
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    I`m bit stumped here and I would need litle bit of enlightning.

    I was under impresion that on Celleron 2 is finaly disabled support for multi cpu work, and that that is reserved for "real" CPUs like PIII.

    So was I under wrong impresion or what? pleas give me answer on this, and explanation, how to enable multi cpu work with celleron 2 or place where I could findout more.

  13. #13
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    Spelling, despite what you've internalized, maybe secondary to Philosophical considerations.

    Back atcha'

    Professur, [sic]

    DMMD

  14. #14
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    For what it is worth, Intel has stated that SMP has been disabled on the Celermines (celeron 2's). However, they generally said the same thing about the celeron, but it wasn't neccessarily the case. Here is my question...

    If Intel knew how to disable SMP support for the celeron 2, why couldn't they have done it for the later productions of the celeron? Obviously it was worth it to them to disable SMP for the celeron 2, so one could conjecture that they would do the same for the current celeron production run. Afterall, they did start clock locking processors in the middle of the production of the P2s, so we know they are willing to change their design in the middle of a run.

    I think Intel probably moved the pin again. There must be a reason why the SMP pin needs a current applied to it, or else they would have broken it off in the current celeron production. Furthermore, if the celeron 2 is indeed basically a Coppermine with half of the cache disabled (a reject Cumine perhaps?), then it should still be SMP capable. I have a feeling that these first runs of celeron 2's will be just that... a modified pentium 3 coppermine, just like the original celerons. Things may change later on though, and I could also just be full of crap.

    Here is one idea though... When someone gets ahold of a celery2, they should compare the number of pins and the layout to that of a coppermine. If they all have the same number of pins, then it would lead me to believe that the SMP pin is still there, just in a different location.

    Just some food for though.

    Ryan

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  15. #15
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    I agree with Ryan
    Though I don't see why they would bother changing the design of the things again, also if they are neutered PIII's why do it? they should just lower the price of them and sell them with full cache!

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