SDRAM vs. RDRAM, Facts and Fantasy

The I/O driver structure of RDRAMs is different than SDRAMs', and RDRAMs do not require that back-to-back reads to different devices incur a gap on the memory bus. Sample timing diagrams for RDRAMs to illustrate that were shown earlier.

An important factor affecting latency is the utilization of the memory system. When it is servicing no other transactions, the latency for an 'isolated' read transaction is different than when other transactions are being concurrently processed. When 2-cycle addressing and levelization are factored in, the system latency for an isolated read is comparable for SDRAM-based and RDRAM-based memory systems.

However, when the memory system is under higher load the answer can be quite different. When one or more additional transactions are being serviced, factors such as bank conflicts and address bandwidth become important issues. The higher bank count of RIMMs versus DIMMs means that the probability of bank conflicts occurring is much lower. Therefore, the high latency and bandwidth penalties associated with bank conflicts occur far less often in RDRAM-based systems than in SDRAM-based systems. Furthermore, as illustrated in the previous timing diagrams, the need for 2-cycle addressing on an address bus used to specify both Row and Column addresses means that the address bus may not be available to start a subsequent transaction in SDRAM-based memory. During periods of higher memory utilization, when more than one request is sent to the memory controller, some memory requests may be delayed waiting for the address bus. For these reasons, under higher loads RDRAM-based memory can be much more efficient, achieving lower latency and higher bandwidth than SDRAM.

So why don't RDRAM-based platforms substantially outperform SDRAM-based platforms on some of today's benchmarks? The answer is that most benchmarks today do not utilize much memory bandwidth. Office applications and even most games are designed to run well on machines that are several generations behind the cutting edge in order to address the largest possible market. I.e., they are designed to run well on platforms with older CPUs and memory (166 MHz Pentiums, for example). The memory technology for Pentium processors was EDO, with less memory bandwidth than SDRAM or RDRAM. If such programs really required high levels of bandwidth from the memory system, they would run well on SDRAM-based and RDRAM-based platforms but poorly on EDO-based platforms, ruling out a large number of potential PC market sales. Benchmarks based on these types of programs thus show almost identical SDRAM and RDRAM performance. In fact, EDO-based systems would probably perform just as well on some of them. Even though memory bandwidth requirements are typically low in most programs today, memory requests are not evenly spaced in time. Rather, memory requests are typically 'bursty' in nature, tending to appear in groups followed by quiet periods with no requests. So although the average memory bandwidth required by a program may be low, during periods of bursty activity, bandwidth requested can be much higher. The high bank count and separate Row and Column address buses make RDRAMs much better suited to bursty communication than other memory technologies.

Skip To Page 1 Introduction 2 Rambus Direct RDRAM 3 Conventional Memory Systems 4 RDRAM Benefits 5 Reducing System Cost 6 RDRAM Pricing 7 RDRAM Pricing Continued 8 RDRAM Performance • 9 RDRAM Performance Continued 10 System Performance 11 RDRAM Power Consumption 12 Benchmark Applications 13 BAPCo SYSmark 2000 14 Benchmark Setup 15 Benchmark Results Intel 440BX 16 Benchmark Results VIA 694X Apollo Pro 133A 17 Benchmark Results Intel i820 18 Benchmark Evaluation 19 Conclusion

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