SDRAM vs. RDRAM, Facts and Fantasy

Many independent reviewers have benchmarked RDRAM systems and compared them to SDRAM systems. Some benchmarks show little, if any, performance advantage for initial RDRAM-based systems. This is often attributed to a high latency inherent to RDRAMs. But what is the latency for RDRAMs, and how does it compare to SDRAM latency?

The answer, not surprisingly, is that access latency depends on several factors, including system architecture and how busy the memory system is. The DRAMs themselves account for only a part of total latency. When the CPU requests data, the request is transmitted across the front side bus and is processed by the memory controller. The memory controller issues the commands necessary to retrieve data from the DRAMs, and the data is passed through the memory controller, across the front side bus, and finally back to the CPU. Differences in chipset architecture, for example, can cause differences in memory latency in systems that use the same DRAM technology.

At the component level, datasheets for both SDRAMs and RDRAMs indicate that access latencies are similar. This is not surprising, since both use similar DRAM cores. But the component-level timings in the datasheets are not the entire story. While most SDRAM datasheets show timings for single devices, when they are put onto DIMMs system considerations change the access latencies. SDRAM motherboards allow for multiple DIMM sockets, but with unbuffered DIMMs the address bus settling time requires that Row and Column addresses be held for two consecutive clock cycles, also known as 2-cycle addressing and mentioned above.

In addition, back-to-back reads to different ranks of devices (which can occur when a double-sided DIMM is used, or when multiple DIMMs are used) require a single cycle bubble on the data bus to ensure that data can be interpreted correctly at the memory controller. This increases latency and reduces bandwidth. Sample timing diagrams for SDRAMs were shown earlier.

In RDRAM-based memory systems, the memory bus can be multiple clock cycles in length, with the memory controller sending commands to the RDRAMs in a wave-pipelined manner. Addresses do not have to be held for consecutive clock cycles as in SDRAM-based PC memory systems, but the flight time of the address and data must be taken into account when determining memory latencies in RDRAM-based memory systems. Because the Rambus channel is routed through the RIMMs, the channel is longer when both RIMM slots are populated than if only the first RIMM slot is populated. From the memory controller's point of view, managing the placement of addresses and data on the channel would be complex if different DRAMs have different access latencies. Instead, the Rambus channel is 'levelized' so that all RDRAMs have the same latency from the memory controller's point of view. This is done during initialization by programming the devices closest to the memory controller with a delay that causes data to be returned to the memory controller with a timing that matches the devices furthest from it. Levelizing a fully populated Rambus channel adds a few bus clock cycles (2.5 ns clock cycles for PC800 RDRAMs) to access latency.

Skip To Page 1 Introduction 2 Rambus Direct RDRAM 3 Conventional Memory Systems 4 RDRAM Benefits 5 Reducing System Cost 6 RDRAM Pricing 7 RDRAM Pricing Continued • 8 RDRAM Performance 9 RDRAM Performance Continued 10 System Performance 11 RDRAM Power Consumption 12 Benchmark Applications 13 BAPCo SYSmark 2000 14 Benchmark Setup 15 Benchmark Results Intel 440BX 16 Benchmark Results VIA 694X Apollo Pro 133A 17 Benchmark Results Intel i820 18 Benchmark Evaluation 19 Conclusion

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