SDRAM vs. RDRAM, Facts and Fantasy
RDRAM Benefits
May 1, 2001
High Bandwidth
RDRAM memory systems use a high-speed bus and a low-swing signaling technology called RSL (Rambus Signaling Level) that allows data to be transferred at high speeds (up to 800 million samples/second) across each wire. The high-speed signaling is performed by dedicated interfaces on the memory controller and the RDRAM. These interfaces are not specific to computer memory systems, but can be placed on any type of chip to speed communication. In this way, Rambus' signaling solution is really a general-purpose high-speed chip-to-chip interface rather than a solution for the DRAM market only. Recently, Rambus has announced design wins in another high bandwidth arena, computer networking.
Efficient Protocol
The high peak bandwidth of RDRAMs (1.6 GB/sec) is complemented by an efficient packet-based protocol and a high bank count that achieves high effective bandwidth. The benefits of the RDRAM protocol and architecture can be illustrated by comparing it to how data is accessed in memory systems that use conventional DRAMs like PC100 and PC133 SDRAMs. The following timing diagrams are for PC100 SDRAMs, but PC133 DRAMs are very similar.
The diagram illustrates two interesting points about SDRAM technology in the PC platform. The first is that in PC memory systems, unbuffered SDRAM DIMMs require ‘2-cycle addressing,’ in which Row and Column addresses occupy the address bus for two consecutive cycles. This is necessary due to the high capacitance of signal traces supporting multiple DIMM slots. Note that in some applications, such as graphics accelerators, where single devices are soldered down to the memory bus, 2-cycle addressing may not be needed. 2-cycle addressing is discussed in the following document.
Intel PC SDRAM Specification PDF
Another interesting point is that the location of data relative to read and write Column commands is different, resulting in a ‘bubble’ on the data bus whenever a write is followed by a read, or when a read is followed by a write.
Another source of performance loss is bank conflicts. Once a bank is accessed, there is a minimum amount of time that must pass before a different row of the same bank can be accessed. Bank conflicts result in a bubble that appears on the data bus, increasing latency and reducing bandwidth.
SDRAM Bank Conflicts
Although not shown, a further loss in performance occurs when back-to-back reads are serviced by different ranks of devices. In order to ensure that data is interpreted properly by the memory controller, a one-cycle bubble on the data bus must separate back-to-back data from different banks of SDRAMs, again increasing latency and reducing bandwidth.
The following diagram shows how commands and data are scheduled on the Rambus channel. The transactions each read and write 32 bytes of data. Notice that the placement of data relative to Column addresses is similar for reads and writes. This means that very little bandwidth is lost when the memory controller transitions from writing data to reading data, and no loss occurs when transitioning from reading data to writing data.
The address lines of the Rambus channel are separated into two groups over which protocol commands are transmitted to the RDRAMs. The first set of address lines is used to specify Row information, while the second set of lines is used to specify Column information. This enhances transaction pipelining by allowing the Row address for one transaction to be transmitted at the same time as the Column address for another transaction. Traditional technologies such as SDRAMs specify Row and Column address over a shared set of wires. This can inhibit transaction concurrency, as conflicts can arise when scheduling the Row address for one transaction and the Column address for a different transaction.
Because RDRAMs and SDRAMs use a similar core technology, their timing characteristics are similar, and the size of bubbles that arise due to bank conflicts are similar. However, bank conflicts will occur less often in RDRAM-based memory systems than in SDRAM-based memory systems due to the higher bank count of RDRAMs. Today, RDRAMs are shipping with 16 ‘doubled’ banks (neighboring banks cannot be accessed simultaneously, so an RDRAM can have up to 8 banks in use at a time), whereas SDRAMs used in DIMMs have 4 banks. The increased bank count of individual RDRAMs over SDRAMs is compounded at the system level by the differences in memory system architecture. Because eight SDRAMs (one rank) respond in unison to each read and write command, there are only 4 total banks for each rank of devices. In a memory system with a single-sided DIMM, there are only 4 banks. In a RIMM, each RDRAM acts independently (only one RDRAM responds to each read and write command), so for an equivalent-capacity RIMM (8 devices), there are 128 banks. The reason that this increase in bank count is so important is that large increases in latency and decreases in bandwidth are caused by bank conflicts. The larger bank count of RDRAM-based memory systems means that the probability of encountering a bank conflict is smaller when using RDRAMs versus SDRAMs. This can have a profound impact on overall performance, especially in PC memory systems that use small numbers of memory modules.
Another feature of RDRAMs is that they employ a different I/O driver than SDRAMs. The RDRAM I/O driver eliminates the need for a bubble on the data bus when back-to-back reads are directed to different devices, reducing latency and increasing bandwidth.
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