SDRAM vs. RDRAM, Facts and Fantasy

The diagram below illustrates a conventional SDRAM memory system in a PC. The memory controller is connected to multiple DIMM sockets through a 64-bit wide memory bus. Address and control signals are connected to the DIMM modules using a different topology than for the data bus, resulting in some signals being loaded differently than others. Row and Column addresses are transmitted on a shared set of address lines, with the memory controller scheduling this resource when multiple transactions are being serviced.

Today, DIMM modules commonly consist of eight 8-bit SDRAMs connected in parallel to compose the 64-bit data bus. All eight SDRAMs, called a bank, operate in parallel performing the same sequence of commands (RAS, CAS, etc) required for reading and writing data. Some DIMMs have sixteen 8-bit SDRAMs, arranged as two banks with eight devices each. One bank populates each face of the module, but only one bank can transmit or receive data at a time. The minimum number of devices in the memory system and the minimum upgrade granularity both depend on the width of the SDRAMs being used. With 8-bit SDRAMs, a minimum of eight devices is required in the memory system to be able to meet the 64-bit databus requirement. This is also the minimum upgrade granularity of the memory system. With 16-bit SDRAMs, a minimum of four devices is required in the memory system, and is also the minimum upgrade granularity. The clock speed of SDRAMs available in PC main memory systems today has reached 133 MHz (with address and data transmitted on one edge of the clock).

A Rambus memory system differs from today's SDRAM-based memory systems in several ways. The memory controller is connected to the RIMM sockets through the Rambus Channel, a set of uniform-impedance transmission lines with a 16-bit data bus. The memory controller incorporates a narrow, high-speed interface called the Rambus ASIC Cell (or RAC) that communicates at high speeds across the channel to the RDRAMs. The RDRAMs also have a high-speed interface that allows them to send and receive data at the same speed as the RAC. The addition of the high-speed interface results in a small increase in die size, but also allows higher performance to be obtained. Address and data are routed in parallel on the Rambus Channel, resulting in uniform signal loading. In contrast to current SDRAMs, memory systems that use RDRAMs transmit addresses and data in a wave-pipelined manner on both edges of the clock.

The Rambus Channel is routed through the RIMM modules and is terminated on the motherboard after the last RIMM module. The Rambus channel requires that all sockets be populated with either a RIMM module or a C-RIMM so that the channel remains continuous to the termination resistors. RDRAMs are also 16-bits wide (some versions are 18-bits wide and use an 18-bit Rambus Channel), matching the width of the data path to the memory controller. Unlike SDRAM-based memory systems, in which multiple SDRAMs transmit in parallel across a 64-bit wide data bus, only one RDRAM transmits or receives data at a time across the 16-bit wide data bus. This means that RDRAM-based memory systems can be composed of a single RDRAM, and have a minimum upgrade granularity of a single device.

In addition, commands are passed along eight control wires routed in parallel to the data bus. The eight control wires are split into a Row control bus and a Column control bus. The Row control bus carries commands such as RAS and Refresh instructions, while the Column control bus carries commands such as CAS and write mask information. Splitting the control bus in this manner enhances transaction pipelining by allowing a RAS operation for one transaction to be specified at the same time as a CAS operation for a different transaction. Traditional technologies like SDRAMs require that Row and Column addresses be transmitted on the same set of address lines, resulting in a resource conflict when the memory system is placed under heavy load.

Skip To Page 1 Introduction 2 Rambus Direct RDRAM • 3 Conventional Memory Systems 4 RDRAM Benefits 5 Reducing System Cost 6 RDRAM Pricing 7 RDRAM Pricing Continued 8 RDRAM Performance 9 RDRAM Performance Continued 10 System Performance 11 RDRAM Power Consumption 12 Benchmark Applications 13 BAPCo SYSmark 2000 14 Benchmark Setup 15 Benchmark Results Intel 440BX 16 Benchmark Results VIA 694X Apollo Pro 133A 17 Benchmark Results Intel i820 18 Benchmark Evaluation 19 Conclusion

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